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Research On Coverage Metrics In Design Verification Via Simulation

Posted on:2004-02-02Degree:MasterType:Thesis
Country:ChinaCandidate:T LvFull Text:PDF
GTID:2178360185996962Subject:Computer system architecture
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As the semiconductor technology keeps moving towards the creation of monster chips, design verification becomes more and more important.This dissertation makes researches on stimuli-generation and coverage metrics in design verification via simulation. We survey productions in research and modern techniques in industry, and apply them in a general-purposed CPU. In the aspect of stimuli-generation, verification via ATPG is applied, and experiments show its value. And in the aspect of coverage metrics, after analyzing advantages and disadvantages of current metrics, many of them are used to evaluate the stimuli in verification via ATPG.It is not computationally feasible to exhaustively simulate designs; therefore, coverage evaluation is indispensable in modern verification flow. Unfortunately, the metrics used so far in current commercial tools have limitation: observability is not taken into consideration, which will result in false confidence. For the observability assessment ones in research, however, the overhead of computing the metrics is very large, and they could not be integrated into simulation tools easily.In this dissertation, we present some original ideas for problems above.1. A new observability evaluation algorithm based on Factored Use-Def chains (FUD chains) is provided. It represents data dependence information of Verilog RTL codes by FUD chains. Furthermore, it enhances capability of FUD chains, by usingĻ†-terms to track running behavior of programs. This idea makes it possible to do data flow analysis statically and dynamically, which is a bridge across the gap of conservatism in compiler technologies and accuracy in verification ones. And, since our algorithm takes variables in original codes as objects to evaluate, it could be integrated with current coverage metrics easily.2. By combining the algorithm above with statement coverage metric, an evaluation system for observability-based statement coverage metric, OCM_Statistics, is realized. The experiment results show that OCM_Statistics enhances capability of traditional statement coverage metric: it is easy to achieve high coverage for statement coverage metric, even 100%, while data evaluated with observability-based statement coverage metric is not so excessively optimistic as the former. It assesses statement execution counts, and checks to see whether effects of possible errors activated by program stimuli can be observed at observed points. So, it will evaluate the degree of verification more accurately. Experiment results also indicate that the observability evaluation algorithm based on FUD chains is significantly more efficient than prior efforts to assess observability information: the overhead of computing the metric by OCM_Statistics is averagely one order of magnitude lower than that of others.
Keywords/Search Tags:Design verification, Simulation, Coverage metrics, Observability, Factored Use-Def chains, Data flow analysis
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