Optimized Technique Of Instruction Scheduling On Godson-Ⅰ Compiler

Instruction scheduling is a very important phase in the back end of an optimized compiler. This thesis is based on the author's work in developing an optimizing compiler for the Godson-I processor, which is a general purpose processor designed by the Institute of Computing technology and discusses three issues related to instruction scheduling: the machine model, the static instruction scheduling and the global delay slot scheduling.Machine model is designed to improve the flexibility and portability of compiler. It encapsulates the information of hardware and provides query interfaces to other components of the back end of an compiler. We discussed several kinds of machine models used in compilers like GCC and Pro64. Then we analyze the machine model of the Open Research Compiler (ORC). Finally we describe the method we use to port the machine model of ORC for the Godson-I processor. Static instruction scheduling decides the execution order of instructions and improves the instruction-level parallelism by reducing stall caused by dependences. We discuss the interactions between static and dynamic instruction scheduling and show that static instruction scheduling is beneficial even the hardware has dynamic scheduling. We also describe the framework of instruction scheduling in our compiler and present experimental results to show its performance.Godson-I processor uses delay slots to reduce the branch latency and penalty of branch mispredictions. It is important for our compiler to take advantage of delay slots effectively. We analyze the scope of delay slot scheduling, present a method to solve possible conflicts in global scheduling of delay slots and improve the selection of scheduling candidates. Then we present a algorithm of global delay slot scheduling. Experiment results show that our approach is effective and robust.