YHFT-matrix Compiler’s Technologies Related To Global Instruction Scheduling Research And Implementation

Matrix DSP processor with independent intellectual property rights and highperformance is researched and developed by the institution of Computer ScienceMicroelectronics of the National Defense Science and Technology University. Theprocessor has strong ability of data computing and therefore can be used in thecommunications of soft base station、underwater sound and so on. In order to exploit theprocessor a correct and high performance compiler is needed. In order to make Matrixcompiler performance become higher, it is more necessary to do the Matrix compiler`soptimizations especially the specific optimizations based on Matrix architecture.According to the characteristics of Matrix architecture several Matrix compileroptimization measures are presented and some of them already have been carried out inMatrix compiler then Matrix compiler`s performance is greatly improved. This paperdescribes the implementation of these optimization measures as follows:(1)Global instruction scheduling based on selection scheduling. Matrix Processoris a VLIW DSP which can execute10instructions simultaneously, so instruction-levelparallelism(ILP) can fully improve Matrix processor’s performance. Instructionscheduling especially the global instruction scheduling is good for compiler achievingILP. According to the selective scheduling based on GCC Matrix compiler has carriedout the selective scheduling algorithm correctly and the improved algorithm accordingto Matrix architecture can achieve higher performance.(2)If-conversion. If-conversion can convert the control flow graph to a data flowgraph, and thus can make successive optimization become more useful especially forthe instruction scheduling. Matrix processor can support Whole Predicate Execution,thus Matrix compiler which develops if-conversion can use the characteristics of Matrixarchitecture better. Matrix compiler has achieved several if conversions based on theGCC added some new if conversions according to particular application. After addingthe if-conversion Matrix compiler`s performance has been further enhanced and afteradding some new if conversions some peculiar programs`speed become faster.(3)Branch delay scheduling. All branch instructions、 jump instructions andfunction calls instructions in Matrix instruction set have four delay slots. If the delayslots are not filled it will cause the pipeline idling and wastes hardware resources. Basedon the implementation of GCC`s branch delay scheduling Matrix compiler implementsthe branch delay scheduling process correctly and the improved algorithm according toMatrix architecture can fill the delay slots more fully.