Instruction-Based Delay Test Generation For Processors

More and more logic is integrated into chips with the rapid development of semiconductor technology. As the speed of microprocessors approaches the gigahertz range, delay test is becoming increasingly critical in industry and receives more attention in research field. With Intellectual Property (IP) based System-on-Chip (SOC) design becoming popular, instruction-based test of processors is a promising method to effectively test the processor cores embedded deep inside a SOC. This dissertation first surveys the recent development of delay test and instruction-based test of processors. The relationship and difference of structural path classification and functional path classification are analyzed. Then, an instruction-based path delay test generation method is proposed for the datapath of a processor. It can apply a processor's own instructions in normal operation mode to test itself without any hardware overhead.The contributions in this dissertation are as follows.1. A new instruction set model is created using dataflow-state matrixs of instuctions. Considering the instruction set architechture and Register Transfer Level (RT-level) description of Processor Under Test (PUT), a dataflow-state matrix is created to record the transition of states and data transfer between registers as each instruction is executed. Based on these matrixes, it's convenient to do path classification at RT-level.2. An RT-level path classification algorithm is proposed based on the extracted dataflow-state matrixes. Paths between registers are classified into Functional Untestable Paths (FUPs) and Potential Functional Testable Paths (PFTPs) at RT-level. Meanwhile, the potential test instructions for PFTPs are recorded, which will reduce the complexity of translating test vector pairs to test instructions.3. A constraint extraction method and a constraint path delay test generation algorithm are developed. Control and data constraints are extracted from the RT-level description of PUT and constraint ATPG is excuted at gate level. In order to extract the control constraints, an instr-state-ctrlsig table is created to store the control signal name whose value is high for every state of each instruction. Two types of data constraints are extracted. One refers to the illegal values of some registers, the other refers to the values of corresponding registers under the control constraints, which are based on four kinds of rules. Finally, a constraint Automatic Test Pattern Generation (ATPG) process for all the PFTPs identified in the PUT, is implemented in a gate-level non-robust path delay test pattern generation tool, by applying the constraints for testing each PFTP respectively to psedo-primary inputs of the combinational network of the...