| MEMS packaging is becoming one key concern with the development of MEMS technology and its commercialization progress. In particular, the requirement for reliable and low cost wafer-level hermetic packaging has not completely met. Wafer-level packaging not only protects the devices from harmful environment, but also prevents the inner micro structures from the possible damage led by dicing step. And the vacuum packaging helps to improve the performances of a wide variety of micro devices ranging from RF switches, micro-gyro and resonators, etc.Upon analyzing some disadvantages of conventional hermetic packaging methods and materials, we introduce a novel wafer-level hermetic packaging technology for MEMS based on Cu/Sn isothermal solidification (IS) technology. After studying the isothermal solidification bonding and reaction mechanism of Cu/Sn binary system, we optimized the Cu/Sn-Cu IS bonding process flow, including Cu/Sn film electroplating and formation, selective dry etching of seed layers, plasma pre-treatment to remove the natural oxide and other matter on surface, the optimization of heating curve and the selection of bonding temperature at 350℃. The wafer-level hermetic packaging was successfully realzed. The quality of packaging was evaluated by X-ray inspection, metallographic observation, electron probe, shear test and hermeticity test. The impacts of the thickness of the Sn film, the structures of the bonding layers and the width of the sealing rings on hermeticity have been also investigated. According to the experiment results, the optimized Cu/Sn-Cu structure achieved the ideal quality, and excellent hermetic packaging can be realized for a sealing ring with a mimimum width of 50 μm. For a successful Cu/Sn IS bonding, a shear strength as high as 27.7MPa and leak rate of around 2×10-9atm cc/s He have be achieved, which can meet the requirement of MIL-STD-883E.And we applied the Cu/Sn IS technology to the fabrication of the micro resonator with a sandwich... |
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