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The Study And Implementation Of Scheduling Algorithm In Low Power VLSI Designs

Posted on:2007-05-04Degree:MasterType:Thesis
Country:ChinaCandidate:W B WangFull Text:PDF
GTID:2178360185486049Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
As the steady growth of chip scale and operating frequency, power is regarded as one of the top concerns including of area and performance in design process. Low power VLSI designs can be achieved at various design levels, which rang from circuit, logic, architecture and algorithmic (behavioral) levels to system level, according to the Down-Top design flow. The effects of low power are significantly different at different levels of design abstraction. The higher is the level of design abstraction, the more early low power designs are considered. So low power designs at the higher levels are able to achieve evident effect.In the paper, we focus on low power scheduling at the behavioral level, which partitions the behavior description into the time interval at multiple voltages and under multiple constraints. This paper presents three kinds of scheduling algorithms: the resource-constrained algorithm, the timing-constrained algorithm and the timing-and-resource constrained algorithm for the case when resources operate at multiple voltages. The resource-constrained scheduling algorithm reduces the power consumption by maximally utilizing given resources operating at reduced voltages and at the same time, reducing the latency. The algorithm is list-based. The timing-constrained scheduling algorithm reduces the power consumption by assigning as many nodes as possible to the resources operating at reduced voltages. In the paper, we propose three kinds of scheduling algorithms with multiple voltages under timing constraints, which have separately lower time complexity, better optimizing effect and better optimizing capability as a whole. The timing-and-resource constrained scheduling algorithm reduces the power consumption by maximally utilizing given resources operating at reduced voltages and at the same time, reducing the latency that satisfies the given timing constraints. In the paper, we propose a Gain-search-based scheduling algorithm under the timing-and-resource constraints, which has better optimizing effect and lower time complexity. Because the scheduling with resources operating at multiple voltages is NP-hard problem, we adopt a heuristic algorithm under the timing-and-resource constraints, which is simulated annealing algorithm (SA). Compared with the...
Keywords/Search Tags:VLSI, HLS, Low Power, Scheduling
PDF Full Text Request
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