The Reconfigurable Logic Research And The SOC Design In The Space Of Symmetric Algorithms

Along with the development of information technology, the electronic governmental affairs, electronic commerce and the distant application of the network in general have been being used widely, the safety of the information exchanged by the network is payed more and more attention to by users. Currently a cipher algorithm is in common used to protect the information transfered. Usually there are two kinds of methods to implement cipher algorithms. The first is realized by software although its' advantage is time-saving and easy to implement,its operation speed is. slow. The second is realized in hardware. The speed of the cipher chip is much more higher than that of a software way. but its algorithm is fixed in the chip, this provides opportunities for the hackers' attack. In this paper, we make use the concept of reconfigurable design to the end of the reorganization in a cipher chip. A reconfigurable cipher chip has higher speed in data encryption, and by changing the control code, it may realize different algorithms in one chip. This means that a reconfigurable cipher chip is superior to the above two ways.Up to date, we can cram as many as one thousand million transistor into one integrated circuit chip. The function of a SOC (System-On-Chip) chip can be very complex. Most SOC design teams have no time and knowledge to design SOC from the very beginning. The reconfigurable efficiency of algorithms is closely-related with that of IP core modules. In SOC design, the dynamic and repeatable use of IP cores has become the key to success of a design.In this design, we analyse symmetric algorithms,and find reconfigurable elements in them. Then we map these elements into IP cores. We verify these IP cores' function with tool of Modelsim, and synthesize in Xilinx ISE, estimate their delay. Based on these work,We complete the frontend design for 3DES cipher algorithm, including simulation and synthesis. The whole design for reconfigurable cipher chip will be completed in later work.