Design And Implementation Of Dynamic Remotely Reconfigurable SoPC Based On Heterogeneous Multi-cores

At present, FPGA-based (Field Programmable Gate Array) embedded systems have been widelyused in aviation, intelligent home appliances, data acquisition, etc. Especially the remote upgrade andmaintenance are extremely important in aviation. Due to the limited hardware resources, people needto reuse them through the static or dynamic reconfiguration. The static reconfiguration terminates theentire system and reduces its capability, but the dynamic reconfiguration can update the systemwithout affecting other running functions. A single-core processor can often handle one task well, butthe heterogeneous multi-core systems can group processors with different advantages and fulfilcomplex computing tasks.This dissertation designs and implements the dynamic remotely reconfigurable SoPC withheterogeneous multi-cores. The hardware subsystem employed the Xilinx EAPR (Early Access PartialReconfiguration) method, and the software subsystem followed the business logic and data separationapproach of the MVC (Model View Controller) framework. The initial design was to break thehardware subsystem into modules. These modules included two reconfigurable IP cores which were a32-bit signed integer adder and a multiplier. The subsystem also included an interface module forconnecting the IP core with the hardware subsystem. The CF card, ICAP, Ethernet interface controllermodules were also designed to support the remote reconfiguration. The paper implemented thedynamic remotely reconfigurable SoPC with a MicroBlaze soft CPU core and these modules. Theheterogeneous multi-cores consisted of one MicroBlaze core and one PowerPC hardcore afterward.The PowerPC processor was responsible for the partial reconfiguration of hardware resources and theMicroBlaze processor supported the verification of the computing by the software program. The paperimplemented the whole hardware subsystem through merging these modules with the heterogeneousmulti-cores, placement, layout and configuration. The front-end Web service utilized technologiessuch as YUI to display page contents and respond to user’s requests. The XHR was used for theasynchronous transmission of Web commands. The designed back-end service was implemented by Clanguage, including the dynamic partial reconfiguration, the multicore interactive authentication, thedocument browsing, the configuration file updating, and etc.Both SoPC systems provide functions like partial reconfiguration with the adder, multiplier orblank module. The systems can also provide remote system upgrading and switching. Meanwhilewebpages display the operations’ response delay and the reconfiguration’s state information. The systems are easy to operate and maintain. Especially, the heterogeneous multicore architecture andsystem upgrade make the scalability stronger and the reconfiguration delay lower. The systems runstable in Virtex5ML507FPGA. The analysis and evaluation of the remote transmission rate, thepartial reconfiguration and Web response delay show that the scheme is feasible in actual remotereconfigurable scenarios.