A Methodology Of Mapping Network Application Onto NP Resources

Due to the complexity and diversity of network protocols, network processor has been widely used in network equipments to meet the flexibility and performance requirements. Network processor is usually treated as a Multi-Processor system on a single chip which contains multiple high performance I/O components and supports high-speed realization of network protocol. NP's programmability brings many advantages compared with ASIC. NP chip has been broadly implemented by Multi-Processor System-on-Chip(MP-SoC) architecture.Designers have to face new challenges when NP is implemented by MP-SoC architecture. With the development of deep sub-micron technology, chip's frequency and integration goes higher, more and more process resource can integrate into a single chip, such as a few of general-purpose RISC processor, various specific co-processor and hardware accelerator, etc. The traditional design method to constructs executable model with RTL language at the first of design is not feasible now. In order to efficiently explore the design space of network processors, the design procedure has to start at more abstract level, yet executable models. Now, a new design method is needed to help designers fix this problem, more concretely is: how to choose all kinds heterogeneous process resource based on network applications and map tasks onto suitable process resource, then form NP architecture and guide NP's early stage design by this.To solve these problems stated above, this paper made deep study on the key technologies and method of mapping network applications onto process resource, and present a mapping method based on genetic algorithm. Firstly, network applications are described by weighted dataflow process network and each resource is parameterized at fist. Secondly, weighted dataflow process network mapped onto parameterized resource. Finally, a network processor architecture model is constructed to evaluate system performance, and guide network processor design at early stage. At the last partation of this paper, we implement SOPC-based network processor prototype in FPGA.