Design And Implement Of Packet Classification Engine Based On Network Processor

The increasing of network scale and performance requires that the network devices of now and future can work at line-speed and intelligently as well as high flexibility. The general CPU and the ASIC can't meet with both of the need. With the well design of architecture and special optimization to the processing unit, network processor can provide a programmable environment for the upper plane, which provides a good solution to the problem of software expandability and hardware acceleration. Network processor is regarded as the core device promoting the development of next generation network.Simultaneously, the development of network information security demands that the routers can support functions, such as policy-based routing, Firewall and Intrusion detection. The key of implementing these functions is the technology of packet classification. As the core of packet classification technology, the performance of packet classification algorithm has a crucial influence on the time delay and throughput of the network.This paper designs and implements an engine system of packet classification applying the parallel classifying algorithm, in which network processor is the hardware core. The major work include:1,Applying the Aggregation to the fields of the rules, a A2BV algorithm is presented based on the ABV algorithm. After statistic and analysis to the present rule libraries, A2BV algorithm reduces the rule fields from five to three, without losing the parallelism of the ABV algorithm. A2BV algorithm has a lower space complexity in comparison to ABV algorithm, while it is more practical being carried out on network processor.2. Applying A2BV algorithm, a high speed packet classification engine is presented based on IXP2400.After analyzing the hardware architecture of IXP2400, we design the software architecture and hardware architecture of an packet classification engine under the Intel IXA frame, also giving the detailed design of function blocks. And it also makes a reasonable assignment among the microengines and memory.3. According to the memory access delay caused by the implement of the A2BV algorithm, an optimization is presented. After analyzing the memory access instruction and its pipeline, we run others microcodes parallel during this delay,this leads to the idle cycle decrease of micro engine.