Processor efficiency for packet-processing applications

Incorporating programmable hardware in a wide variety of network routers is a subject of current investigation in academia and industry. Small, all-software routers, for example, employ programmable hardware to serve customers at network end-points: general-purpose platforms serve as inexpensive solutions for these low-end routers. At the other end of the spectrum, large network routers, which have historically used hard-wired platforms for high performance and given each packet the same "best effort" handling, are beginning to include some customized programmable hardware to meet a growing need for specialized packet handling. Programmable hardware provides greater flexibility than hardwired platforms and allows large routers to offer packet processing with more runtime variability as well as new or updated packet services.; Large routers can benefit from added flexibility, but they must continue to support their high volume of traffic. Although a wide range of designs using programmable hardware to supply the combination of performance and flexibility for packet processing have been proposed and implemented, no dominant approach has emerged. In this dissertation we have evaluated a comprehensive set of techniques for mapping work to an array of processor cores, and several methods for managing the resources of an individual processor. We present work to show that specific characteristics of our application domain can be leveraged to increase the efficiency of programmable hardware and manage the contention for hardware resources.; We employ a concrete model of a hardware platform and an application composed of a chain of dependent tasks to demonstrate that packet-processing applications in our domain can best use a processor array by exploiting the inherent data parallelism available in the independent packets in the network traffic. We identify the four potential benefits available to the less efficient task parallel implementations and explore ways to provide three of those benefits for our data parallel implementation. We present analytical models which predict performance based on key system and application characteristics and evaluate performance sensitivity to available hardware resources and virtualized hardware contexts.