Research On DFT Techniques For High-Performance General-Purposed Processors

With recent advances in process technology and rapid growth in the density of integratedcircuits, high-performance general-purposed processors are confronted with challenges suchas high reliability, high quality, low cost and short time-to-market. Meanwhile, how to test thecircuit efficiently with reasonable test cost has become a much more difficult task. To improvethe testability of circuit and to reduce the test cost, many different design-for-testability (DFT)techniques have been proposed.To ensure the quality of chips and to reduce the test cost are the main objectives of DFTtechniques. However, the increased density of circuit has resulted in a tremendous increase intest data volume which leads to high test cost. When the process scales down into deepsub-micron, the necessity of delay test also exacerbates the test data volume problem becausethe number of delay test patterns is much larger than that of traditional stuck-at test patterns.Since test compression provides a good solution to this problem, it has drawn significantattentions of academies and industries and has become an important component of DFTtechniques.This thesis investigates different DFT strategies adopted in mainstream processors inindustry and introduces their applications to a high-performance general-purposed processor.As for the test compression, this thesis conducts researches in test stimulus compression andintroduces several typical types of compression methods in the literature. On this basis, anovel method is presented in which the decompressor is implemented by combinationalcircuit. The major contributions of the thesis are listed as follows:1. Investigations on advanced DFT techniques for processors. By learning DFTapproaches from different types of processors in industry, this paper introduces variousDFT techniques, including internal scan design, built-in self-test, test point insertion andboundary scan design. In addition, it summarizes the challenges of DFT techniques in thefuture.2. Applying different DFT techniques to a high-performance general-purposedprocessor chip. In this processor design, internal scan design, built-in self-test andboundary scan design are combined to test different types of faults effectively. And theattainable fault coverages are all satisfactory.3. A new test compression method is presented. This thesis introduces some typical testcompression methods and proposes a new test compression approach. The proposedcompression architecture drives a large number of internal scan chains with far fewerexternal input pins, thus delivering significant reductions in test data volume. Thismethod exploits the large number of don't care bits (X) in test cubes and analyzescompatible relationships among scan slices. Experimental results on ISCAS89benchmark circuits indicate that the proposed method can reduce test data volume by90% while inheriting the benefits of reducing test application time frommultiple-scan-chain design.4. Analysis of the compression effect of broadcast scan. Since broadcast scan is awell-known compression structure, this thesis estimates its compression effect byapplying it to an IP core. Its effectiveness and applicability are demonstrated byexperimental results.