Design And Implementation Of Processing Element In Network Processor

Along with the rapid increase in network bandwidth and the emergence of variousinnovative applications, the network processor, which adapts massively on-chip parallelcomputing and with sophisticated programmability, is drawing people's attention and widelydeployed by industries. Nowadays most network processors consist of multiple programmablePEs (processing elements) working in parallel. The micro-architecture and topology of PEsignificantly impact on both the performance and the programming model of the networkprocessor. This dissertation focuses on the design and implementation of PE in networkprocessor. Based on analysis of the network applications, the traits of various applications areabstracted and mapped to hardware resources. With those features bearing in mind, theparallel multi-processing scheme, which consists of array of PEs, is selected as the underlyingarchitecture of our network processor. A concise and efficient PE structure is developed, andspecialized for the actual requirements and design constraints. We take the ASIP (ApplicationSpecific Instruction Processor) flow in prototype implementation and verification. Severalbenchmarks that feature the processing in network applications are applied on our prototypedesign. Performance evaluation and hardware budget are also done through analysis of datacollected from simulation and implementation.The PE proposed in this dissertation highlights features as follows: 1) The MIPS I(Microprocessor without Interlocked Pipeline Stages) instruction set is reduced andcustomized for network processing. In the design, we trim off the interrupt/exceptionmechanism, CP0 (Coprocessor 0), MMU (Memory Management Unit) and some ALU(Algorithmic and Logic Unit) operations involving large overhead in timing, area andcomplexity. 2) An efficient and scalable pipeline is designed with 5 pipe stages, which mimicsthe structure of MIPS R2000/3000. To aid the extension for operations with long delay and togain more performance, we add interlock signals and bubble squash mechanism to the pipestages. 3) A shared instruction memory scheme is proposed with global multi-banking pseudomulti-port and local dual-port, the probability of collision is dramatically reduced and thebandwidth of instruction stream is assured. 4) The interfaces with MAC controller, sharedmemory pool and scratch pad are implemented to enable a complete design. We also developthe mechanism of communication and synchronization between PEs to enable efficient packetprocessing.After modeling the PE and prototype network processor in RTL (Register TransferLevel) using Verilog HDL, we verify the design and demonstrate the feasibility of theproposed architecture through FPGA prototyping. In a platform built with Xilinx 2VP30, asingle PE takes 1680 4-input LUTs (Look-Up Table) and can run at 86.8 MHz. The networkprocessor with 4 PEs takes 90% of the logic resources in the FPGA with capacity of 3 millionsystem gates, and runs at 66.7 MHz. We also evaluate our design through preliminary ASICimplementation. When using UMC .18 μm standard cell library, the single PE will take anarea of 0.213 mm2 and can run at 350 MHz, while the logic synthesis tool used is DesignCompiler from Synopsys. When 18 PEs are integrated into a network processor, it can provideenough processing power for OC-48 and fulfill the requirement of high-speed trafficconvergence at the edge.The results of prototyping show that the proposed design is concise, with less hardwareresources, and can reach high frequency at the same time. The structure is suitable formassively integration on a single die and can provide enough power for high speed and deeppacket inspection.