An OPC-Friendly Maze Routing Algorithm

OPC is widely employed in deep sub-micron IC manufacture, to alleviate the distortion of printed silicon image. However, the current design flow does not take OPC into consideration during physical design stage. This might result in mask patterns that cannot be corrected by OPC. Thus, we propose an OPC-friendly maze routing algorithm, which links fast lithography simulation with an enhanced maze router, to guarantee the success of OPC and to ease the heavy burden of OPC.