Design And Research On Graphics Controller For Handheld Devices

Graphics controllers are widely used in many graphic and display equipments. Recently, focuses are put on the implementation and optimization of graphics controllers in handheld devices. The size, power and cost for handheld decices need considering carefully. The small size LCD graphics controller is discussed in this paper used for image display and process. SRAM is embedded for display buffer which stores the display data. The 2D graphics accelerator is designed to accelerate the image move, copy, fill and color expansion. Besides, the JPEG hardware codec, YUV/RGB convertor, camera interface, and image resizer are embedded for photo function. Based on the analysis of function and architecture of graphics controllers in LCD display system, this dissertation presents a front-end design of a graphics controllers chip and FPGA verification with TOP-Down design topology. The graphics controllers chip can process and display clearly and stably on LCD Panel. Image controller, BitBLT engine, and JPEG codec are the most important part in graphics controller system. This paper describes the architecture of BitBLT engine and JPEG codec embedded in graphics controller for handheld devices. The VLSI design of BitBLT engine, and JPEG codec are presented. DA (Distributed Algorithm) in DCT/IDCT transport and Huffman encode and decode algorithm are researched and analyzed, so the best algorithm will be designed to reduce chip cost, improve chip frequency and simplify circuit's redundancy. Focuses are put on band-width design, techniques for multi-clock design, memory arbitration logic, and implement of color expansion. The design of graphics controllers is implemented by trade-off between speed, power and area. The results of the simulation and FPGA verification are presented. It is a very high speed VLSI Design through the pipeline architecture with power optimization. In the paper, the RTL code of graphics controllerchip is described by using Verilog HDL. In succession, the function verification and logic simulation by Synopsys VCS 6.0.1. Finally, the FPGA verification is presented, which is implemented with Xilinx ISE Series 5.2i and FPGA Virtex-2Pro-vp40-fg1152-4. Through the logic and function verification, the graphics controllers are proposed to meet the expected performance requirement of the system.