IP-DSLAM Design Based On FPGA

Many of the next-generation solutions being deployed today are already beginning the migration from traditional circuit-switched ATM-based networks into Ethernet/IP-packet-switched architectures. DSLAM technique has developed from the first generation with pure ATM DSLAM to the second one with ATM core and IP uplink architecture, which is more adaptive to the IP WAN. To improve the reliability and efficiency, the third generation called pure IP-based DSLAM comes out. A conversion between ATM and IP packet is implemented on the line card. Some mature techniques are combined together appropriately. It's an innovate in techniques.The third generation DSLAM implements a transparent transmission between ATM and Ethernet frames. It can be design by software. But the performance is not satisfied commonly. The FPGA gives a high-performance, low-power and cost-effective solution. The IP DSLAM designed by FPGA provides more flexibility and lower risk. First, this paper introduces the requirement of IP-DSLAM, gives a design block diagram. Then appropriate chips are selected. Detailed modules are divided. At last it analyzes the processing flow of the IP-DSLAM deeply.Logic low level design of every module is described in this paper, according to the ADSL Uplink and downlink. Based on the transparent transmission of the protocol, some functions such as MAC address binding, IP address binding and VLAN are also introduced.At the last of this paper, the application and development of IP-DSLAM is discussed.