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ASIC Implementation Of Multilevel Filter Algorithm For Small Targets Of Infrared Images Detection

Posted on:2006-11-01Degree:MasterType:Thesis
Country:ChinaCandidate:J W SunFull Text:PDF
GTID:2178360182969181Subject:Pattern Recognition and Intelligent Systems
Abstract/Summary:PDF Full Text Request
Multilevel filter algorithm for detecting the small targets of infrared images, which can obtain different band filters by changing the cascade number of the basic filter template, can detect different small targets. An architecture is proposed on the basis of discussing the multilevel filter algorithm. According to the requirements of external system, we propose the design requirements and typical application and discuss the internal realization mechanism of structure at length. Two kinds of filter templates--1×5 and 1×7 are composed by concatenating the 1×3 basic filter. Algorithm can process the larger small targets using Gauss Pyramid for Multiresolution and effectively decrease the gray-value of targets and noises. There are 3 data channels in datapath and accordingly detect three kinds of small targets--3×3, 5×5 and 7×7. Pipeline technology is used in each data channel. In order to improve the process speed, substitute the shift-and-add circuits for multipliers in datapath. Fixed point calculation is implemented with the precision of 8bits. This architecture can process 8-16 bits data. The emphasis of this thesis is the implementation method of datapath. The question about how to improve the precision is enlarged upon, and one way for improving the precision is also put forward. We also state the state-machine of fifos and input and output signals of each state. Completed the circuits design using Register Transfer Level method. Passed the function simulation, and analyzed the error in detail. Stated some relative concepts, environments and constraints setting in logic synthesis. Compared the differences between two phases of STA. Simply introduced basic steps of physical design, and especially put forward an effective resolvent for multi-clock network distribution. Some parameters of multilevel filter chip: throughput capacity---5M-10M Pixels/s; internal frequency---50MHz; image size to be supported---128×128, 256×256, 320×240.
Keywords/Search Tags:Multilevel Filter, ASIC, Small Targets Detection, Synthesizable Design, Static Timing Analysis
PDF Full Text Request
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