Peripheral Design Of AVS Decoder Chip

As the common base standard in digital audio and video industry, the digital audio video coding standard has a great amount of requirements in information industry. Since the start of this new century, with the great progress made in technology of encoding and decoding and the rapid development in IC and computing technology, the digital audio video coding standard is facing with a historic opportunity. The AVS(Audio Video Coding Standard) standards for the current world advanced level. The implementation of AVS101-a high definition decoder chip is a import milestone of the industrialization of AVS and is very significant to the development of video audio industry. The main object of this thesis is to resolve the Peripheral Interface of the Decoder core and its verification, including the stream input/output interface, frame access interface and AV interface etc., which are PCI local bus interface , DDR SDRAM interface, I2C, I2S, CCIR/SMPTE interface respectively. Because of the constraints of our FPGA development environment, we design the PCI90xx local bus interface to match the PCI90xx-serial PCI-bridge chip in out FPGA development board. The I2C interface is used to control the video encoder chip-ADV7311.The design of I2C master interface is also covered in this thesis. DFT(Design For Test) and physical design are also introduced in this thesis. The design mentioned in this thesis has been functional verified in a XILINX FPGA(Virtex II Pro VP100) and successfully taped out in SMIC.