A Investigation Of On Chip Parasitic Parameter Extration

With the VLSI technology getting advanced, the cross talk between layout sign and power ground line is becoming a significant factor in influencing VL SI performance. And the power/ground lines are among the mostly influenced lines. To analyze the crosstalk and noise effect, the first step is to get the resistance, capacitance and inductance, which means the parasitical parameter extraction. Since the resistance can be calculated by formula way with an acceptable error, my aim in this paper is focused on the capacitance and inductance extraction.In this paper, we first laid some effort on the numerical capacitance extraction method. We put a divide and conquer method based on numerical method into practical. And after that, we develop a Iibrary-look-up method which shows us a good result. Additional, we do some investigation on inductance extraction and fulfill the Inductwise extraction method with some improvement.