The Overlap-Combination Approach To Chip-Level 3-D Capacitance Extraction

The application of SOC (System On a Chip), radio frequency circuits andwide-band wireless communication techniques promotes the development of GHznano-scale digital and digital-analog mixed integrated circuits. The increasingdemand of delay analysis makes parasitic capacitance extraction of interconnects playa more and more important role. Nowadays, high precision analysis of delay requiresthat conductors on the chip should be divided into many smaller blocks to extracttheir full, distributed coupling capacitance matrix. However, existing 3-D numericalcomputing methods are not efficient enough to extract these parameters of the wholechip directly and precisely.This thesis implemented the extraction of full coupling capacitance matrix inchip-level, based on the hierarchical block boundary element method (HBBEM). Themain contributions include:1. Implementation of overlap-combination approach for 3-D chip-levelcapacitance extraction while using the hierarchical block boundaryelement method (HBBEM) as field solver. It cuts the whole chip throughtwo directions, x and y, into large amounts of smaller-scale regions(window and overlap region), and then combines the capacitancematrices for all regions to get the full capacitance matrix. The proposedmethod achieved sufficient accuracy while greatly reducedcomputational cost, so it makes chip-level accurate capacitanceextraction possible.2. Analysis of computational accuracy and efficiency of theoverlap-combination method. Based on experience of actual layouts,several principles are proposed in how to choose overlap region andwindow.3. Extension of HBBEM reuse technique. It further improved thecomputational efficiency.4. Parallelization of the aforementioned method. Two task-assigningalgorithms are used to parallelize this overlap-combination method.Parallel computing experiments were carried out on both multi-processorworkstation and heterogeneous workstation clusters, and achieved highparallel efficiency.All the algorithms above have been implemented. Several numericalexperiments with actual layouts demonstrated the efficiency, reliability andhigh parallel efficiency of the proposed method.