The Research And Realization Of Digital Down Conversion Technology In Software Radio

The advantages of Software Radio include the flexible function, the open structre and the low cost.Because of this,more and more national research institutions and companies pay attention to Software Radio.Due to the limitations of the poor processing speed of current hardware, the IF signal which is sampled by the ADC device must be reduced the samling rate by the Digital Down Converter to be processed by the general DSP devices,The Digital Down Conversion has great impact to the performance quality of Software Radio system,so the Digital Down Conversion Technology has become one of the core technologies in Software Radio.The sampling theory and multirate digital signal processing theory were introduced first,which were the basic theory of DDC.The circuit structre of the DDC has been researched,and the main factors which impated the performance quality of DDC were been discussed.Two common menthods to realize NCO were been introduced,while the efficient decimation filter group in DDC were researched in this thesis. The DA algorithm is a commonly used algorithm to realize MAC in FPGA,which avoid the use of multipliers. The high-tap FIR generally adopted DA algorithm, so the improvement and the implementation of the DA algorithm based on FPGA were researched in detail in this thesis.Based on the reaearch of the digital processing theory and the circuit structure of DDC,the DDC was been designed and realized using FPGA. DDC was been sub-module,and each part circuit was designed using QuartusⅡsoftware of Altera corporation.Each part circuit and the whole DDC system was simulated using Modelsim software.The filter paraments were been designed, and the spectrum of the simulation outputing data was been analyzed using Matlab.The NCO based on CORDIC algorithm was realized,which has 16-stage pipelines.The CIC filter was designed,whose highest extraction is 32.The two-stage decimation HB filter was designed.The high-tap shaping filter with 102 orders was designed, when the inputing data is 16-bit,it only need 8 clocks to complete once filter.Finally,each circuit was connected to realize the DDC system.The maximum extraction rate of the DDC system is 128,and the DDC system used about 9752 logic elements of FPGA.