High Performance Video Development And Verification Platform

Video coding technique is developing fastly in these years. A very short period of the development of VLSI is required for competition reasons. The FPGA based development and verification systems are very useful for many applications consider of its low-price and fast verification. With the development of video coding standard, the complexity and density of the video codecs are much higher than before. There is clear demand for high-performance FPGA based video development and verification system.This article introduces a FPGA based high performance video development and verification platform. This platform is designed based on the original MPEG-4 video codec ASIC development system. The high performance video development and verification platform aimed at H.264 high 4:4:4@4 or AVS Jizhun@6.2 etc. video standard at high level. It support the resolution of 1920× 1080(4:4:4). The key features for the platform are listed as follow, obviously they are designed for high performance video codec developing: Large and high speed programmable logic Large and high speed memory High speed data transaction port Support different type video in/out ports Provide plenty of test ports and tools Provide interface application models More compatibilityThis article also introduces the development process of AVS D1 decoder and the AVS motion vector prediction model (AGU) on the high performance video development and verification platform. The software and after-implementation verification processes of the AGU are also introduced. Finally, comparisons of synthesis with the same constrain are given among the MPFG-4 codec development system, high performance video development and verification platform and SM1C 0.18μm cell library.