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The Hardware Design Of Parallel Processing System Based On DSP And FPGA

Posted on:2012-10-10Degree:MasterType:Thesis
Country:ChinaCandidate:M Z ZhangFull Text:PDF
GTID:2178330338991427Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Along with the unceasing development of digital signal processing technology, the embedded system information processing requirements of most areas are increasing, also new strong-function and high-performance digital signal processors launched. Mononuclear processor can achieve 1.25GHz core frequency, and has rich of high-speed memories and peripherals interfaces, but with the increasement of communication, image,etc algorithm complexity, also the requirements of signal processing quality and real-time are more sophisticated and strict, a single processor core has not been enough to meet the processing requirements, so the design of high-speed parallel processing system based on multicore DSP or multiDSP is essential.The performance of embedded system hardware platform mainly depends on the performance of main processing module, the bandwidth of interconnection interface and interconnection topologies. This design implements a high-speed parallel processing system based on TI latest high-performance multicore DSP processor TMS320C6678 and logic chip XC5VLX110T, which has excellent core processing performance and interconnection interface with high data transmission capacity. Considering the uncertainty of the object, the system needs to have certain versatility and extensibility.This topic relies on the actual project application. Designed four DSP parallel processing system being responsible for processing complex algorithm is one part of the whole system.The printed circuit board used in this design adopts standard size of 6U, and connects to high-speed backplane through CPCIE connectors , realizing system interconnection and expansion.This system design based on DSP + FPGA system architecture, adopts the loose coupling interconnect way, and configures independent high-speed external memory for each DSP and FPGA, processors whole interconnect based on high-speed serial interfaces(Hyperlink, SRIO) can implement arbitrary reconstruction among processors in the system. Chose interconnect scheme overcomes interconnect bandwidth bottleneck problems based on traditional bus tight coupled system, also makes full use of FPGA rich high-speed interface resources , improving the system expansion ability.The design involved core frequency and interfaces rate can be up to GHz, moreover the package of chose chips is the form of BGA, with high pin numbers and densities, So the requirements to PCB design are extremely strict, need to consider signal integrity, power quality and dissipation, this design adopts 14 layers PCB to implement the high-speed parallel processing system.This paper detailedly introduces the high-performance multicore processor TMS320C6678 and high-speed interconnecting interfaces, provides specific system scheme and hardware schematic design ,introduces the relevant contents of high-speed PCB design, and completes 14 layers PCB. Moreover to guarantee the availability and stability of this design, I also made simulation and analysis to the PCB, realizing the multi-DSP high-speed parallel processing system hardware platform based on high-speed serial interface.
Keywords/Search Tags:TMS320C6678, XC5VLX110T, HyperLink, signal integrity, eye diagram
PDF Full Text Request
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