Design And Realization Of Ultra-High Speed Data Sampling And Real-Time Processing System

Linear Frequency Modulation (LFM) signal is one of the most frequently used large Time-Bandwidth Product signals in modern high resolution radar systems. Usually the echo signal is processed in real time after be Stretched. Comparatively, direct intermediate frequency sampling and real-time processing such as pulse compressing can realize much wider dynamic observation scope and is more flexible to realize. According to the requirements of processing LFM signal in a radar system, this paper proposes and designs an on chip system which can realize the direct intermediate frequency sampling and real-time processing.By employing two channels of the AD08D1500 Analog-Digital Converter (ADC), the system has an ultra-high sampling speed of 3Gsps with 8-bit resolution and its actual effective number of bits is larger than 6. Sampled data is buffered in DDR2 SDRAM. In order to preparing for the expanding of the sampling system, this paper analyses the algorithms that can estimate and modify the offset, gain and time phase mismatches among the channels which are used to composing a time interleaved ultra-high speed sampling system.Sampled data is processed in real time on FPGA, including pulse compression and CFAR target detecting. Pulse compressing is implemented in frequency zone. FFT and IFFT operation are realized via using a FFT IP Core which can deal with as most as 65536-points data. The multiply operation is realized by hardware multiplier. More sophisticated architecture is proposed in this paper, it can reduce 70% of the pulse compress time needed in this system. CFAR target detecting is used to detect and store the target relevant information in pulse compression result and abandon useless data, which can ease the press on following processing system. Hardware realization plans were proposed for ML-CFAR, OS-CFAR, double threshold detecting and mono-pulse range cell integrated detection algorithms.Sampled or processed data is able to be transmitted quickly to PC or other workstation via PCI Express interface or optic fiber interface respectively. Parameters of the system are able to be set via the human-machine communication interface on the PC software.The control logic and data processing operation of the system are implemented on one FPGA, designed following the principle of SoC, which makes its functions can easily be changed or updated.