The Application Of Cascaded Encoding And Decoding Module Based On FPGA In 936C Image Transmission System

With the rapid development of digital multimedia technology, more requirements of high quality and real-time of video images are needed when transfer information. As the transmission channel is not ideal and the noises exist everywhere, the signal received by the receiver has some inevitable errors which decline the images'quality. So we can take the way of channel coding to improve the reliability of information transmission.In order to further improve 936C video image transmission system's property, this paper proposes an error correction program of concatenated code with interleaving technology which integrated three kinds of coding and decoding technologies, which are RS codes, packet interleaving and convolutional codes to correct errors. This main work and contributions of this study are as follows:1. It uses Z228 image processing chip to do MPEG4 compression coding for the dynamic video images that captured by the digital camera, and completes the hardware circuit designing of image compression and playback.2. It represents the RS codes, packet interleaving, convolution codes'encoding and decoding principles, provides the design project of the whole channel's encoding and decoding module and develops a real-time channel codec by using Xilinx's XC3S2000 chip.3. It has resolved the encoder bit rate matching problem by setting a receiving buffer in the encoding and decoding module. Through the RS decoding process it improves the decoding efficiency by applying the pipelining mechanism.4. In the Viterbi decoder designing, it adopts the new ACS designing method to avoid the branching measures'overflow and reduce the consumption of hardware resources. Then in the decoder output unit it takes an improved traceback method, using 4 RAM to traceback at the same time, improving the decoding rate.5. It cascades the image compression encoding and decoding module, 2-channel codec and the data frame processor to form a baseband processor platform for the real-time image transmission system, and completes all the hardware's designing and FPGA-channel encoding and decoding algorithm's software designing.In the project, the correctness and reliability of the algorithm is verified through making FPGA simulation experiment on the baseband processing unit of 936C real-time image transmission system, and the data throughput rate of channel codec reaches to 100Mbps. In the whole system'test, the baseband processing unit's property meets the designing requirements.