Research And Implement Of Low-Power And Configurable NoC Router

With the reduction of the chip area, the acceleration of computing and the increase of communications bandwidth, an increasingly prominent issue of power dissipation has been becoming one of the key factors restricting the development of NoC. The dynamic power dissipation of NoC mainly consists of the power of the routers and on-chip networking, therefore, to design a low-power router has important practical significance.for reducing the power dissipation of NoC.This paper focuses on the design of the low-power and configurable NoC router which can apply to the NoC with the two dimensional regular topology, such as 2D Mesh, Torus, Fat-Tree and Butterfly Fat-Tree, after researching on the design concept of configurable router and the low-power design techniques of SoC. The router is designed with Verilog HDL and simulated by Synopsys EDA software. The function verification and performance analysis of the router base on a 4×4 2D-Mesh NoC and a 4×2 FT NoC separately.The key technologies of NoC router design and the low-power design techniques of SoC are proposed firstly. On this basis, the paper presents the design scheme of the low-power and configurable NoC router. During the design of the configurable router, we adopt the virtual channel technique to avoid deadlocks, parametric buffers, an improved source routing algorithm and an arbitrator mechanism based on Lottery, all of which help increasing NoC router flexibility. On the other hand, during the design of the low-power router, we adopt the clock-gating technique to optimize the power dissipation of the router input and the segmented matrix crossbar to replace the fully connected crossbar by analyzing the power dissipation of the submodule of the router.The main work of this paper provides a platform for both the design of the adaptive routing algorithms and the further study of the NoC performance based on the different topologies.