CMOL Cell Assignment And Defect Tolerance

With the decrease of intergrated circuit (IC) feature size, the current silicon-based microelectronic devices have entered the nanometer range. However, the high fabrication cost and quantum mechanical effects make the traditional IC design methodology which consists of CMOS device, Boolean logic and lithography techniques can hardly endure the challenge. For the sake of extending the Moore's Law, researchers have proposed some nano/hybrid circuit architectures which integrate the advantanges of nano-crossbar and conventional CMOS technique. Among them, CMOL (Cmos / nanowire / MOLecular hybrid) is regarded as the most promising technique that may replace the CMOS. The high integration density and low fabrication cost caused widespread concern by IC communities. Nevertheless, the lack of researchs about computer aided design tools for CMOL seriously hinders the industrialization process. Based on this situation, the paper proposes efficient cell mapping techniques that considers the architecture features of CMOL. The proposed method is validated by experiments on benchmark circuits. Generally, the paper is made up of following aspects:1. Regarding the connectivity domain constraint of CMOL, the cell mapping task is formulated as an optimization problem. By appropriate encoding scheme of CMOL layout, the problem is solved by Genetic Algorithm (GA) which consists of two-dimensional croosove, mutation operators with the objective function to minimize the total wirelength. The best result obtained when the algorithm teminates is the mapping layout of CMOL. The experiment results show the proposed algorithm has advantages in circuit scale over previous approaches.2. Considering the slow convergence speed of GA , the paper introduces Lagrangian Relaxation technique to decompose the complexity of the mapping problem. Simulantously, the Simulated Annealing (SA) based local search algorithm is introduced for better exploring the solution space. The hybrid optimization algorithm has performance improvement on CPU running time, area and delay.3. Considering the high-fanout gates lead to difficulty in mapping. The logic replication based equivalent transformation method is introduced for splitting the high-fanout gate. By finding the high fanout reference value and formulating a quadratic equation, the circuit after transformation can easily be mapped in CMOL array and has better timing. 4. Regarding the ubiquitous defect and fault in nanoelectronics, the paper analyses the main souce and models of defects. In addition, the prospects of defect tolerance of CMOL are also demonstrated.