Research On Area Optimization Of Mixed Polarity Reed-Muller Logic Circuit Based On Fireworks Algorithm

With the rapid development of the electronic information industry,people have higher and higher requirements for the performance of electronic products,which forces the integration of circuits to be higher and higher,so the number of transistors in electronic chips become larger and larger,which will directly lead to the area of electronic chips increase.In the current pursuit of small integrated circuit design area and low power consumption,it is urgent to solve the problem of how to reduce the area of electronic chips.In the past integrated circuit research,researchers mostly developed circuits based on Boolean logic.A large number of studies have shown that Reed-Muller(RM)logic circuits based on AND/XOR or OR/XNOR have better results in terms of area,power consumption,and delay.For a fixed-polarity RM logic circuit with n input variables,there are 2n different polarities,that is,its optimization space is 2n:for a mixed-polarity RM logic circuit,it has 3n different polarities,that is,the optimization space is 3n.Therefore,mixed polarity has a larger optimization space and performance optimization potential than fixed polarity.This article starts from the mixed polarity RM logic circuit,and studies the circuit area optimization problem in depth.The main work of this paper is as follows:1.Area optimization of MPRM logic circuit based on ternary fireworks algorithmAiming at the fact that the existing fireworks algorithm is not suitable for solving the combinatorial optimization problem of three-value discrete,this paper proposes a ternary fireworks algorithm.The ternary fireworks algorithm is mainly used to solve the combinatorial optimization problem of three discrete values.The algorithm encodes the individual fireworks population in ternary system,and improves the mutation operation in the traditional fireworks algorithm.The algorithm fully inherits the advantages of the traditional fireworks algorithm,such as bursting,diversity,distribution and parallelism,and enhances the algorithm’s performance in searching the optimal solution.In addition,an area optimization method of MPRM logic circuit is proposed in this paper.This method searches the optimal polarity of MPRM logic circuit based on ternary fireworks algorithm,so as to realize the area optimization of MPRM logic circuit.Experiments based on MCNC Benchmark circuits show that,compared with the MPRM logic circuit area optimization algorithm based on genetic algorithm,its average circuit area is reduced by 44.46%.Compared with the MPRM logic circuit area optimization algorithm based on discrete particle swarm optimization algorithm,the average circuit area is reduced by 34.66%.2.Area optimization of MPRM logic circuits based on multiple disturbance fireworks algorithmAiming at the problems that traditional fireworks algorithm and ternary fireworks algorithm are easy to fall into local optimum and low search precision in the process of searching for optimal population,this paper proposes a multi-disturbance fireworks algorithm.The multi-disturbance fireworks algorithm inherits the advantages of fireworks algorithm and ternary fireworks algorithm.At the same time,the Latin hypercube sampling method is introduced to initialize the population,and the secondary perturbation is introduced in the process of iterative optimization of the algorithm,so that the algorithm can quickly jump out of the local optimal,so as to find the global optimal solution more efficiently.In addition,an area optimization method of MPRM logic circuit is proposed in this paper.This method searches the optimal polarity of MPRM logic circuit based on multiple disturbance fireworks algorithm,so as to realize the area optimization of MPRM logic circuit.Experiments based on MCNC Benchmark circuit show that compared with the MPRM logic circuit area optimization algorithm based on ternary fireworks algorithm,the average circuit area of the proposed algorithm is reduced by 7.4%.Compared with the MPRM logic circuit area optimization algorithm based on genetic algorithm,the average circuit area of the proposed algorithm is reduced by 53.34%.Compared with the MPRM logic circuit area optimization algorithm based on discrete particle swarm optimization algorithm,the average circuit area of the proposed algorithm is reduced by 44.12%.