The Realization And Optimiaztion For PowerPC Embedded System Simulator

With the rapid development of the embedded applications, embedded system simulator technology also has been developed every day. In embedded systems simulator, instruction set simulator is the most widely used development tools in the field of embedded system, it can assist the designer verify that the new processor design, compiler design and verification, and support the operating system and debugging system and so on. Although in the circumstances without real hardware, developers can simulate implementation process about the hardware, which reduces the cost of R & D process.POWER is a microprocessor architecture which developed by Apple, IBM, Motorola AIM league. In 1991 PowerPC processors have the excellent performance, lower power consumption and low heat dissipation and have widely used in the embedded space. But the cost based on the PowerPC system is more expensive than X86 PC, so it is very necessary to develop and research the PowerPC embedded systems simulator. This paper achieves the simulation and optimization for PowerPC E600.The main work of this paper for PowerPC includes: Firstly, simulate the instruction e600 set of PowerPC processor using type of explain simulation, including branch instructions, data processing instruction, the program status register (PSR) transfer instructions, Load/Store instructions, abnormal interrupt instruction; Secondly, in order to improve the performance of instruction set simulator, this paper using the dynamic translation technology which based on pseudo instruction to optimize the instruction set simulator ,and achieved dynamic compilation with no specialization and dynamic compilation with specialization. Based on the pseudo instructions of dynamic compiled simulation technique, which means during compile time generate pseudo instructions translate into intermediate code, each pseudo instruction includes two things: one is a pointer to a semantic function; another is the necessary arguments from the decoder, which will be used in semantic function. In this way, the time consuming decoding process from run time is moved to compiled time, so the speed can be improved. Finally, using cyclic algorithm, encryption algorithm, sorting algorithm to verify the functionality and performance of the instruction set simulator.