Data Acquisition And Convolution Processing Hardware System Design Applicated In Ultrasonic Imaging

Ultrasonic imaging technology, which is safe, non-invasive and good in real-timeimaging, is widely used in medical diagnosis and treatment. At present Ultrasonicimaging is one of the three modern medical imaging technology, the other two ofwhich is X-ray Imaging Technology and Isotopes Radiation Diagnostic Technology.High-Frame-Rate Ultrasonic Imaging System has some advantages such as beingfast and high frames, thereby having wide application prospect. The all-digital designscheme for the High-Frame-Rate Ultrasonics Imaging can be realized easily, andreduce the cost of the system, enhance the flexibility of the system. At the same time,it can lay the foundation of the establishment of the general platform for ultrasonicimaging experiments.High speed data acquisition system is one of the key moduls in all-digitalhigh-frame-rate ultrasonic imaging system. Data acquisition system acquires theanalog signal, then caches the data, and provides the reading port for datatransmission system. In this dissertation, a design scheme of the high speed dataacquisition system is introduced. The design uses AD9228 for data sampling, usesFPGA for recieving the digital signal output then completes serial-to-parallel. Afterthat FPGA realizes data caching function with controling the SRAM.In ultrasonic imaging, the implementation of the algorithm is very important.Usually, this assignment is completed by software in computer. Implementing thealgorithm in FPGA hardware platform can improve the speed and decrease theworkload of software, thereby enhancing the performance of the imaging system. Inthis dissertation, a design scheme for realizing the convolution computing in FPGAhardware platform is discussed. This scheme realizes the 256 bytes convolution.The entire design introduced in the dissertation is comprised by three parts:1.The PCB design for high speed data acquisition system, including schematicdesign and PCB design.2.The FPGA logic circuitry design for high speed data acquisition system. Theentire data acquisition system is completed by configuring the FPGA.3.The implementation of the convolution computing in FPGA hardware platform.The convolution is completed efficiently using FPGA.Through repeated revisions and tests, the high speed data acquisition system canwork at acquisition and caching rate of 40MHz, providing a reliable data acquisition scheme for High-Frame-Rate Ultrasonic Imaging System. The design for 256 bytesconvolution can work at 87KHz, satisfying the requirement of medical ultrasonicimaging.