A Hardware Design Of IEEE1588 Precision Clock Synchronization Protocol

With the rapid development of internet technology, more and more applications demand higher accuracy of frequency and clock synchronization. Because of the high cost and political and security hidden danger in using GPS the idea of passing frequency and clock signal by ground wire transmission link arises at the historic moment. With the absolute advantage in high precision and solutions that reduce the influence of shaking delay in network, IEEE1588 precision clock protocol gets more and more attention and widely used in communication network.The background of clock synchronization demand and the domestic and overseas research situations are introduced at first. Expound the principle of PTN packet transport network, compared advantages and disadvantages of several clock synchronization technologies that are commonly used in PTN network. Then analysis the PTP agreement which is described in the IEEE1588 clock synchronization standards in details. Study the IEEE1588 system structure and PTP equipment types and PTP synchronization mechanism. Based on above researches, a hardware implementation scheme of frequency and clock synchronization is proposed. And realize the whole circuit with verilog hardware design language. After that the design and general realization of each module of the clock synchronization circuits is provided with structure diagrams. Finally, a test platform was build, the design was verified and validated. After placement, routing and optimized using QuartusII, the design is expected to run at a frequency of 200MHz and speed of 5Gbits/s.There are three features in this design: firstly, it supports both frequency synchronization and time synchronization, while the previous designs usually support only time synchronization. Secondly, this design supports both one-step mode and two-step mode. Because of the realization complexity, other designs only support one-step mode. In this paper, a method of quick match of sourceportID and sequenceID through grouping storage and read at the same time to compare is provided, so that it can support both one-step and two-step mode. Thirdly, a pipelined structure is adopted in the hardware realization of the design to guarantee every 11 clock dealing with a message, thus fulfilling the frequency and speed requirements.