Design And Implementation Of Key Modules Of Cryptography Accleration Engine Using FPGA

Cryptography acceleration engine SOC is a newly developed cryptography technology which integrates the advanced methodology of SOC designing and existing hardware encryption technology. Compared with cryptography coprocessor, cryptography acceleration engine SOC has not only higher security integration but also better adaptability. It has good application and development prospects. The modular exponentiation module is the necessary part in almost all kinds of cryptography acceleration engine.Montgomery Modular Multiplication(MMM) is one of the ideal algprithm for implementing modular exponentiationin hardware. This thesis proposes an improved MMM on the base of existing results. The new algorithm is optimized for hardware implementing, and is suitable for resource efficient designs. Then we implement the algorithm in a Xilinx FPGA of VirtexII family. The result of synthesis shows that the IP core takes merely 467 CLBs in FPGA device and can finish exponentiation operation in a time under 40ms.Besides the modular exponentiation IP core, a SHA-512 IP core is also designed and implemented through analyzing the FIPS-180-2 standard.Leon2 processor IP core is chosen to be the basis of the cryptography acceleration engine SOC. The IP core is optimized through cutting the cache subsystem in it. The optimization results in a reduction of 10.5 percent in the FPGA unit consumption of the processor. It also leads to nearly 60 percent decrease in the amount of BRAMs used by the system.In the end of the thesis an implementation of cryptography acceleration engine SOC using FPGA is introduced. The implementation includes the resource efficient modular exponentiation and the SHA-512 IP core and the optimized processor IP core. It can conduct a series of public key algorithms containing modular exponentiation.