Design And Implementation Of RSA Chip Based On CIOS Algorithm

With the rapid development of computer and network technology, it is widely recognized that security issues will play more and more crucial roles in the future information systems. The conventional symmetric cryptography pays more attention to the Confidentiality and Availability of information, but the neoteric cryptography thinks that the Authenticity, Integrity and Non-repudiation are more important in commercial application.Public-key cryptography, which was presented, in eighty ages, can efficiently solve the problems such as key distributing and Non-repudiation obtaining, which exsit in conventional symmetric cryptography. RSA is a successful public-key cryptography algorithm in theory and application, the core operation of RSA is performing modular exponentiation with very long integers, nowadays, the safe length of RSA key is 1024 bits, which recognized by international.This thesis studies on the implementation of 1024-bit RSA chip on FPGA deeply. The main work are as follows: the basic Montgomery algorithm is analyzed, the advantages and disadvantages of it's modified algorithm CIOS and FIPS in hardware implementation are given out; By adopting high-radix architecture and using 32 bit parallel multiplier which presented by Altera LPM library as the core operation module, a kind of modular multiplier architecture design is proposed; Besides it. single modular multiplier is used and the serial binary exponent scan algorithm from left to right is adopted. The RSA modular exponentiation operation with very long integers completes by time-sharing transferring modular multiplier. The final implementation of 1024-bit RSA cryptography chip is based on Altera FPGA EP1C6Q240C.At the utmost clock of 86.01 Mhz. our 1024-bit RSA implementation's encrypt/decrypt rate is about 24kbit/s. 3054 LEs and 8 M4K memory blocks are used. Compared with previous works our proposed architecture is the most resource-save RSA hardware implementation on Altera FPGA.