The Design And Implecation Of Transmitter's Circuit In SDH Networks Analyzer

SDH network analyzer is an instrument which can test SDH networks and SDH device. It should be designed in strict accordance with ITU-T G.707 requirements and other related agreements to meet the vast majority of mapping and multiplexing paths of SDH, so as to achieve the function of detecting a variety of SDH paths and equipments. As the SDH transmission technology has been widely used in the world, and is still at the core of metro in many countries, the SDH network analyzer provides SDH network maintenance personnels and equipment manufacturers a stable, reliable and rich detection tool for their maintain, production and R & D. SDH network analyzer's hardware circuit mainly includes three parts: transmitter,receiver and other public hardware platform. The receiver and transmitter circuit plays a vital role in the wholeSDH network analyzer system, while the performance of theirs reliability and stability directly affect the efficiency of the instrument. This dessertation is to study hardware design and implementation of transmitter circuit in SDH network analyzer.This dessertation analyzes the working principle of SDH network analyzer, studies the ITU-T G.707, ITU-T G.704, ITU-T G.783 and other SDH-related protocol, specifies functional requirements and technical indicators for transmitter circuit in SDH network analyzer, and thus defined design and debugging scheme for transmitter circuit.According the design scheme of transmitter circuit, this dessertation specifies detailed design structure and module partitioning, completed hardware (RTL) design for the transmitter circuit with Verilog HDL, including the design and implementation of the SDH section overhead modules, higher-order path overhead modules, low-order channel module, PDH overhead module, pointer adjustment modules and so on.This dessertation also establishes the simulation platform with HARNESS structure. Combined with the receiver circuit of SDH network analyzer, transmitter circuit is simulated by NC-VERILOG simulation tools, traversing a variety of TEST_CASE for simulation. The errors found during the simulating are modified in time. Simulation and modifications have been repeated until the correct functions are obtained.Finally, the design was implemented by FPGA after RTL simulation. Based on the hardware platform provided by the partner, the FPGA is installed on the system board and board-level verification and debugging is done, so as to complete debugging with the external circuit, docking with other companie's SDH network analyzer, and docking with the SDH equipment for testing.