Embedded Visual Inspection System And IP Core Design Based On FPGA

With the rapid development of the technology of integrated circuits and computer vision etc, A new detection technology has been emerged--Image detection based on computer vision technology. In the monitoring process, As large amounts of data need to process, request high real time and often include sophisticated algorithms such as segmentation, detection, marking, identification, therefore, these tasks are usually acomplished with multi-processor architecture in embedded real-time system. With the system integration requirements continue to increase, meanwhile, the FPGA performance and integration are greatly improved, the problems such as large amount of data, processing speed does not match, low reliability and poor accuracy can be solved easily when using FPGA to handle the digital signal. A embeded visual inspection system is designed on one chip using the xilinx FPGA platform based on sopc technology in this paper, which include image processing algorithms, embedded technology and multi-processor parallel processing technology, to achieve acceleration processing in real-time video capture, image detection. The main research contents as follows:1. According to video standards, a video capture IP Core based on the interface of IPIF is designed using Xilinx EDK, the top software control the IP core via the bus interface and obtain the image imformation from the standard video stream through DMA mode.2. By analysis the preprocess theory which based on template calculate, a image preprocess IP core based on template calculate is designed by Xilinx DSP48 slice, to achieve the rapid processing in algorithms based on template calculate such as image filter, sharp and edge detection etc. The IP core connect to the system using FSL as a coprocessor, offer rapid template compute, and support the max template is 5X5.3. According to wavelet transform theory, a wavelet detection expedite IP core using finite impulse reponse filter(FIR) is designed to achieve real-time wavelet decomposition or recomposition. Wavelet expedite IP core connect to hardware system as a coprocessor, can be realize acceleration of various wavelet operator via configuring the lter coefficients from top software.4. A dual-processor coordination program is design Based on Xilinx's lulti-processor architecture and uCOSII operating system, to achieve parallel image rocessing task; and propose a access method between the dual-processor and )processor. According to the experimental result, analyze the key factors of achieving te acceleration with multi-processor.5. Modify the Scheduling strategy of uCOS_Ⅱto support time-sharing task mctions...