Software Optimization And Hardware Accelerator Design On NoC-based Multi-core Processor

With the appearance of multi-core technique, the development of processor has been raised to a new step. The multi-core technique can not only make system deal with tasks concurrently, but also expand the system easier, and at the same time the system can be integrated more powerful performance in a small shape which will use lower power and produce fewer heat. So there is no doubt that the multi-core technique will provide a wide space for the development of processor in the future.During the development of multi-core processor, a new architecture called Network on Chip (NoC) is received more and more attention. The core idea of NoC is transplanting the technique of computer network into the field of chip design, which will replace the tradional bus structure. NoC has extreme advantages in scalability, reusability, design efficiency, bandwidth, synchronization strategies, so it is one of the most promising solutions of the communication problem on the chip.This thesis embays the technique of multi-core processor based on NoC, and unfolds the discussion from two aspects of software optimization and hardware accelerator design. The main work of this thesis are as follows.First, we detail some key technique of NoC. Second, combining with H3MP-16 multi-core processor which is designed by our research team, we introduce its architecture of software and hardwate, and discuss design and optimizatiom of fade in fade out algorithm detailedly. Because of the need of hardware design, we analyse and compare some string pattern matching algorithms which is used in deep packet inspection (DPI), as well as some hardware realization methods of DPI. At last, we discuss a hardware realization scheme of a certain string pattern matching algorithm and its result of simulation, and at the same time, we give two assumptions of combining the scheme with our H3MP-16 multi-core processor.There is a question that should be pointed out. The various realization methods of DPI can be divided into two parts. On the one hand, some methods focus on the hardware realization, and on the other hand, some methods would like to use the multi-core processor to complete all the tasks. In this thesis, we try to combine the hardware realization with the multi-core processor, which can be seen as the special point of this thesis.