Research On Hardware Acceleration Processing Technology Of Visual Recognition Based On ARC Processor

With the gradual landing of artificial intelligence from concept to industrialization,more and more industries have begun to integrate with AI,giving rise to new vitality.Complex vision processing and analysis in embedded machine vision front-end equipment is an inevitable development trend,which places higher requirements on the computing performance of embedded vision systems.The specific image processing algorithm is designed as a dedicated hardware accelerator,which is integrated in the embedded SOC,and the required functions are implemented entirely through hardware logic.Increasing the concurrency of image processing calculations through hardware parallelism can greatly improve the data throughput and image processing and analysis capabilities of embedded machine vision systems.The solution of adding a dedicated hardware accelerator to a machine vision system based on a low-cost general-purpose processor can not only improve the vision processing capability of the embedded vision system,but also maintain the flexibility of the system.Therefore,the research on hardware acceleration of embedded machine vision system is of great significance.In order to solve the needs of visual recognition applications,this paper studies the hardware acceleration technology of visual recognition algorithms based on the ARC HS embedded multi-core processor platform.The main work and contributions are as follows:First,this paper studies the software and hardware co-design method and the ARC HSDK embedded development platform and the HAPS-DX prototyping system for rapid verification of hardware design.In order to improve the performance of the embedded front-end for face detection and recognition processing,the functional requirements and overall framework of the ARC HS processor-based face recognition hardware acceleration system are proposed,and a hardware acceleration scheme based on the multi-core ARC processor platform is designed.Then researched the Adaboost face detection algorithm based on Haar features and Eigenface,Fisherface,LBPH three face recognition methods.Based on the Open CV open source computer vision library,a test experiment of the detection rate of the face detection algorithm and the recognition rate of the face recognition algorithms is performed on a PC,and a test experiment of the detection and recognition speed is performed on the ARC HSDK platform.It is found that the face detection algorithm seriously affects the real-time performance of the system.A hardware acceleration implementation of the face detection algorithm is proposed.Then,the software and hardware collaborative design ideas are used to design and optimize the parallel structure of the image reduction module,image sub-window integral graph calculation module and Adaboost cascade classifier module in the hardware accelerator of Adaboost face detection algorithm.After that,the AXI4 bus interface of the hardware acceleration module is designed to meet the need for efficient communication with the embedded platform.Using the AXI Tunnel interface,the bus communication interface between the embedded platform and the hardware algorithm module is established,and the interface communication driver based on the Linux system is designed to meet the need to access the hardware acceleration coprocessor at the software level.Finally,with the FPGA-based HAPS-DX prototyping system,the software and hardware coverification of the visual recognition system is performed,and the function and performance measurement are studied on the face detection hardware accelerator.The experiments show that the ARC HS processor-based face recognition hardware acceleration system can complete the expected face detection and recognition functions.And in the 640*480 resolution image input,the detection speed of face detection hardware acceleration is up to 11 times higher than that of software.