Design Of LNA And PA Based On RF CMOS Process

With the rapid development of wireless communication technology and the constant advancement of modern CMOS technology, making the implementation process based on CMOS radio frequency integrated circuits (RFIC) to be more widely applied to low-cost, low power, small size, high integration, multi-standard, multi-band direction.The traditional realization of RFIC in GaAs, BiCMOS technology can now be achieved in CMOS technology ,which has advantages in integration with digital baseband circuits, and lay a good foundation for realization of a System-on-Chip(SoC). Therefore, this is based on a CMOS process design work in 900MHz/1900MHz dual-band low noise amplifier and high efficiency of work in the 2.4GHz Doherty power amplifier.Firstly, this thesis introduces the subject of background, research significance and the research situation at home and abroad of dual-band low noise amplifier and Doherty power amplifier. On the basis of relative references, the thesis gives analysis to common-used structures for input impedance matching, classical two ports noise theory and MOSFET two port noise parameters, power-constrained noise optimization procedure for low noise amplifier. Then, in order to save area, inductance improvement of technology can be adopted. And to reduce power consumption, the thesis adopt the current reuse and analysis several current reuse topological structure, which pointed out the merit and demerit and improvement of structure. Input and output impedance matching can be dual-band analysis. With a supply voltage of 1.8V, the simulation results show that the dual-band LNA has the power gains greater than 16dB, noise figure less than of 2.8dB and good input and output matching.Secondly, the thesis gives analysis to the performance parameters of power amplifier, power amplifier type of work and improved the efficiency of several technologies. Then, Doherty power amplifier is proposed. So, on the basic principle of Doherty amplifier technique is analyzed and summarized. For linearity of Doherty power amplifier, the bias voltage of main amplifier and auxiliary amplifier is analyzed by the value of gm3. In order to increase Doherty amplifier voltage capability, we describe the mechanism of oxide breakdown and hot carrier effect and its effect on Power Amplifier design. As for the two challenge of CMOS technology, the designed 2.4GHz Doherty Power Amplifier in the dissertation which power stage uses the thick MOS transistor and the drive stage adopts self-baised Cascode structures. Compared to traditional self-bias structure and improved self-biased structure, results show improved self-biased common-gate transistor (M2) of the Vgd relative to the traditional structure of the common-gate transistor (M2) is reduced by 22%. With a supply voltage of 3.3V, its power gain is 18.6dB, power added efficiency is 46.6%, with 26.6dBm of output power at P1dB. From the input power 1dB compression point back 6dB of power added efficiency is still 31.3% and output power is 22.8dBm.Finally, the circuits layout are designed, detailed overview of layout should pay attention to the rules. Then, for the layout of low noise amplifier and Doherty power amplifier to do a specific design.