The FPGA Design Of Direct Digital Frequency Synthesizer Based On Piecewise-Polynomial Approximation

The most critical block in a direct digital frequency synthesizer(DDS) is the phase-to-amplitude conversion. In order to reduce the DDS output spurious and resource consumption, enhance the performance of DDS,we must adopt effective and optimal phase-to-amplitude conversion. This paper presents a new technique to implement a DDS with the phase-to-amplitude conversion block using piecewise-polynomial approximation instead of the ROM LUT. The hardware kernel of this design is EP2C8Q208C8 of Cyclone II series FPGA made by Altera Inc.In the whole design, firstly, establish the corresponding mathematical simulation model of the piecewise polynomial approximation to verify the algorithm and calculate the parameters of each segment according to certain criteria in the MATLAB environment. Then complete the design of DDS in Verilog HDL.Design and verify the module of phase accumulator,quadrant converter, phase-to-amplitude conversion and the timing between modules. The process use IP multiplexing, in order to improve computing speed using the pipeline technique.At the same time modularize and parameterize the circuit,so that it has a certain degree of generality. When changing the segments and orders of a polynomia with only a small number of parameters need to be modified can be realized. In the FPGA system-level simulation, the paper presents a Quartus II Simulation with MATLAB software, this way imports the simulation of the output waveform data into MATLAB to compute and verify the correctness of the design results by a graphical form. With a external DAC module, we can realize the Physical verification of the DDS system.Finally, the performance and resource consumption are compared with the approach of the ROM LUT architecture, the results show that the method significantly reduces the ROM table resources. At the highest clock frequency is almost the same, in order to achieve the same SFDR index (78dBc), ROM look-up table structure consumes 210×11 bits ROM resources and 83 logic elements, our method consumes 192 bits ROM resources and 590 logic elements.