The Design And Implementation Of High-performance DSP Level-two Cache Controller

DSP(Digital Signal Processor) is a kind of processor for digital signal processing, which has been applied widely in many fields, such as communication, military and household appliances.With the rapid development of integrated circuit technology, compared to the microprocessor, the memory access speed improvements slowly,the performance gap between microprocessor and off-chip memory becomes the bottleneck.Now on-chip caches are widely used in order to solve this problem.The main research work is to design and implement a kind of the DSP Level-two cache controller.This thesis analyses the G1000 DSP architecture and two-level memory structures, and does some research on the modern cache design techniques.The author has completed the design of L1P, L1D, and L2.L1P can only be read by CPU,which is the level 1 program cache .L1D is a two-way set associative cache,which implements a least-recently used (LRU) line allocation policy.It has a write buffer between L1D and the L2 memory.If there is a write miss,the data is written to the write buffer which not need to be written to the L2 immediately.The level 2 unified memory (L2) can operate as SRAM, cache, or both.It maintains the coherence between the L1P/L1D and the external memory system by the snoop commands. The design has been logic verificated, and the results show that the design can achieve a variety of functions, each module can work properly.