Data Cache Design, Multi-machine System

The work in this thesis is part of National Defense Preliminary Research Projects--"the research of the design of the 32 bit microprocessor used by the newgeneration of battleplane (Long Teng R2)", NO. 41308010108. By studying RISC architecture and exploring design methodology, aim at design embedded 32-bit microprocessor compatible of PowerPC instruction.The embedded 32-bit microprocessor "Longtium R2" is compatible with instruction set and interface timing of PowerPC 750 microprocessor. The architecture is full copyrights. Using the Top-Down methodology, synthesis with SMIC 0.18μm library, the clock cycle is less than 4ns. It also implemented on Altera EP1S80 FPGA and the third part applications have been successfully run on this Prototype processor.This paper firstly discusses the Design and Verification of Memory Management Unit and Cache Unit, and later performs in-depth study of the high-speed Cache Coherence problem in multi-processor environment. In reference to PowerPC750,the Cache Coherence Protocol named MEI Snooping Protocol that could be applied to "Longtium R2" Microprocessor is proposed and implemented.Comparing with other snooping protocols, the test results prove that the protocol effectively lowers down the request numbers to BUS and Memory, therefore leads to significant performance improvement. The research work of this dissertation mainly includes:1. Performs systematic research on Memory Management and Cache Control in the High Performance Microprocessor. Then the Memory Management Unit and L1 Cache that are compatible with PowerPC Instruction Set are designed and implemented. The simulation results and analysis prove that it is fully compatible with PowerPC750 in function.2. Studied the current hardware implementation methods that solve the High Speed Cache Coherence;and performs quantitative analysis and compare. Based on the study, this paper designs a Data Cache Coherence Protocol named MEI Snooping Protocol that could be utilized for "Longtium R2" Microprocessor and realizes the snooping control, therefore effectively solves the High Speed Cache Coherence problem of the "Longtium R2" under multi-computer environment.3. Performs in-depth research on verification methods, and comes up with one unique verification method for "Longtium R2". Direct and random tests areperformed to complete the verification of Memory Management Unit and Cache in single-processor environment.4. Built a SMP simulation model. Verification of Data Cache Snooping protocol was performed in multi-processor system.