Implementation Of The Key Algorithms In H.264/AVC Based On FPGA

As a new video coding standard, H.264 has excellent compression performance and good network compatibility, while its computation complexity is much higher than common encoder. Though the H.264 video coding system can be realized by software,it is difficult to meet the requirement for real-time applications due to the algorithm complexity. As a result, the real-time realization of H.264 faces great challenges. The efficient and feasible VLSI architecture for H.264 encoder chip also becomes the hotspot of ASIC design because of the market perspective for H.264 applications.This dissertation has conducted the research focusing on the algorithm and its VLSI architecture design of the key technologies in H.264. The contributions of dissertation are mainly listed as follows: Firstly, the new features of H.264 different from the previous standards are introduced.Then, detailed analyses of the two algorithms of Discrete Cosine Transform & quantize and Context Based Adaptive Variable Length Coding in H.264 baseline profile are made. Finally, high efficient architectures based on FPGA for the two algorithms are presented. In order to decrease the complexity of the design,the complicated modules are divided into several simple modules by the modular thinking. Pipeline processing techniques and parallel processing techniques were adopted to increase the throughput of the system. Replacement of zig_zag scan for reverse zig_zag scan results in a great rise in efficiency of CAVLC module. Arithmetic operation was used to replace static code tables to reduce memory consumption in CAVLC module. All hardware circuits are described by Verilog HDL, are synthesized by using synthesis tool-Synplify, are fittered and assembled by using ALTERA Quartus II, and are verified by using ALTERA Cyclone II EP2C35F484C6 FPGA. The results indicate that the hardware designs of the key algorithms are feasible. The transform & quantize module has as high a maximum coding system frequency as 157.01 MHz, and the CAVLC module has as high a maximum coding system frequency as 146.43 MHz.The design has laid a good foundation for the development of H.264 codec chip. So far, the Verilog HDL code design and simulation test of the transformation quantification module and CAVLC module have been finished, but there are still many works left to perform a system prototype.