The Research And Design Of CMOS RF Power Detector

With the rapid development of mobile communication technology, the emitting power control modular is becoming an indispensable part of mobile system. As a core of emitting power modular, there is a necessity of study on radio frequency power detector.Based on the theory of CMOS circuit, the dissertation not only has studied various radio frequency power detector in domestic and foreign widely, but analysed their advantage and disadvantage as well, on the base of absorbing these achievement, a radio frequency power detector is designed that stratifies a criterion of TD-SCDMA and LTE. Based on the TSMC 0.18 m CMOS technology, the power supply is 1.8 volt, the circuit is simulated under Cadence and the layout is finished by Virtuoso. The entire circuit is consist of RMS testing modular and direct current logarithm amplifier modular, worked at the frequency between 1-5GHz, and has 30dB dynamic testing range and a testing error less than 1dB, power consumption is 0.6mW,which satisfies the requirement of the system above.The design project in the dissertation has the character of big bandwidth, low power consumption, and long detective range. In order to decrease the influence of mismatch and realize wide output swing, source in common differential structure is adopted in RMS. Direct current logarithm amplifier is composed of operational amplifier and exponential current feedback modular. In order to decrease input noise and satisfy wide input range, current mirror load structure of PMOS transistor input is adopted in operational amplifier input class, simultaneously, it can reduce system power consumption by utilizing the characteristic of sub-threshold of MOS transistors in exponential current modular. The dissertation has analysed the short-channel effect under the deep sub-micron technology in detail. Finally, the entire circuit has been simulated, which validates the design project, and accomplished the layout.