| This thesis presents a low current, large bandwidth envelope detector that facilitates integration into the architecture of CMOS radiofrequency integrated circuit power amplifier (RFIC PA), and meeting the requirements for application in modern communication technologies specifications, such as LTE carrier frequency and LTE-A bandwidth. The envelope detector is intended for PA efficiency improvement-related control functions. The small die area of the envelope detector allows its easy integration into a CMOS PA IC, and the use of a novel embedded calibration function for output voltage swing adjustment ensures convenient interfacing with the required control circuitry. Measurements from a fabricated 0.18 mum CMOS integrated circuit, which includes a 6000 mum2 die area for the envelope detector, demonstrates performance of a 110 MHz bandwidth with a DC power consumption of 2.3 mW using a 1.8 V supply voltage. The envelope detector is designed to present a high input impedance, therefore ensuring that the detector implementation in the architecture causes a low performance degradation of the PA line up. This is demonstrated with the implementation of an RF system that includes a PA output stage, with the designed detector coupled to the PA input.;The second aspect of this thesis is the characterization of an RFIC CMOS 0.18 mum amplifier transistor array in terms of biasing level, gain, delivered output power and efficiency. The characterization highlights relevant informations which are intended to assist the scientific community when designing a full RFIC CMOS PA line-up. The RFIC CMOS amplifier transistor array is operated in the class AB region, at 1.88 GHz using a 3.3 V supply voltage. Experimental measurements show a gain of 13.7 dB at low power, an output referred 1dB compression point (P1dB) of 19 dBm and an efficiency (PAE) of 17.4 % at P1dB. |
