The Design Of A 16-Channel-Led Driver IC With Constant Current

In recent years, with the rapid development of the optoelectronic technology, microelectronics, computer technology, communication technology and image processing technology, it leds to the emergence of large screen LED display system, and because of its high brightness, colourful, good reliability, the use of long life, environmental adaptability, and low cost advantages, They are widely used in many fields such as advertising, securities, transportation, sports and other fields .The LED display applications require specialized LED Driver IC, which allows LED to obtain uniform and stable current, so that it makes the LED display more even, to meet the application requirements on various occasions, and also can extend the LED 's life. Extensive use of LED displays, it promotes the development of LED constant current driver chip , and also have higher requirements for its.In this thesis, a 16-channel-LED driver IC with constant current is designed . It is designed with UMC's 0.35CDMOS process supply voltage ranged in 3～5.5V. The output current range of each channel is 2mA～90mA and is precise regulable. In this design, the current match between each channel is ? 1.5% typically. It is ? 3% between chip and chip typically. The voltage of output can withstand 17V to meet the needs of series of multiple LED. The frenquency of the data clock is 25Mhz,it can meet high speed data transmission. The whole design, including bandgap reference module, current regulation module, power-on reset module, the thermal protection module, input and output port modules, the output stage module and the digital logic control module.In this paper, based on the analysis of principles of the multi-channnel constant current LED driver chip, and under the guidance of the analysis of the specific performance, we did sub-circuit design and simulation, the overall circuit co-simulation and analysis, And describes the placement and routing, design and verification of the layout. Finally the post-layout simulation was done. Through the analysis of test data, the chip achieved better function, more in line with SPEC, and has a smaller chip area.