Hardware Transactional Memory Architecture

With rapid development of chip design techniques, Chip Multi-Processor(CMP) has been the first choice for the architecture designer to improve the performance of the system. This architecture has created an unprecedented opportunity to exploit parallel programming, so synchronization or ordering mechanisms for accessing the shared data among mulitiprocessors should be required to guarantee mutual exclusion. Nowadays, traditional parallel programming model usually utilize a set of primitives, such as locks and condition variables, which bring the problems such as deadlock, priority inversion and the complexity of parallel application. Consequently, it becomes difficulty for designer to optimize the parallel computing performance.Transactional memory (TM).is a unique mechanism to handle concurrency challenges in shared-memory chip multiprocessors. The programmer-defined transactions are provided as the. fundamental unit of parallel tasks,which guarantee the atomicity, consistency and isolation. This novel mechanism can substitute for the complex lock mechanim, simplify programming model, and improve the parallel-programming productivity and performance.This paper propose and implement the hardware transactional memory based on the architecture of RISC/DSP processor——MediaDSP64. The hardware architecture such as transactionnal register file, transactional memory cache, transaction priority controller, data conflct detector and so on should be designed. Moreover, the transaction instructions and hardware transaction execution model are proposed. The hardware transactional memory is implemented in both FPGA hardware verification platform and software verification platform. We utilize the ticket booking system and scientific algorithm to be the benchmark to do some research on the following aspects, such as the key technique of the transactional memory mechanism(data version management, conflict detection management), the programming model, the transactional memory evaluation methods and so on. The correctness of the hardware transactional memory mechanism is verified on these platforms.