Implementation Of Simulation And Compilation Of Transactional Memory In Multi-Core Processors

Multiple processing cores being integrated into a chip become the most important way of improving processor's performance. It can decrease the power cost and increase parallel computing performance of processor, without increasing the processor's frequency. However, to make full use of parallel computing performance in multi-core processors, the greatest challenge is parallel programming model. Nowadays locks are used to keep parallel threads synchronized, but may lead to deadlock, priority inversion and other mistakes, and also make the performance hard to optimize. In the transactional memory model, a series of shared memory operations are regarded as a transaction, to ensure atomicity, consistency and isolation. It can replace the lock, simplify programming model, and improve the parallel computing performance.This thesis will introduce a derivative of software transactional memory(Buffering Software Transactional Memory, BSTM), which implements write buffer, and imports hash table and message passing policy into the structure for optimizing the BSTM structure. The experimental results indicate the model brings significant advantages compared with other implementations.And we also implement a simple transformation tool, translating C++ code with transactional grammar into standard C++ code. The later can be compiled with standard C++ compiler and linked with BSTM library. This implementation makes BSTM library completely transparent to the programmer, and simplifies programming with transactional memory model.