Design And Implementation Of The PIC Detector In Code Division Multiple Access System

In the CDMA communication system, multiple access interference (MAI) is a main factor that impacts the systematic performance and capacity.How to reduce this kind of interference has become a hot research topic recently.In multi-user detection, various kinds of available information is fully used to carry joint detection on the users to be detected. Multi-user detection not only can mitigate the influence of MAI, but also can inhibit near-far effect to some extent, which further explores the development potential of CDMA communication systems.This paper mainly researches on the implementation of multi-user detection algorithm based on FPGA. Firstly, the internal structure and the development design process of FPGA are introduced in detail. Several methods of data flow control are stated with actual design instance. Secondly, the paper discusses the structure and process of the algorithm for partial interference cancellation, based on Hebb learning rules. From the point of hardware design of FPGA, this algorithm is disassembled and simplified. Finally, the FPGA design and implementation of partial parallel interference cancellation based on Hebb learning rules are finished,verifying the correctness of the design.Combining the detector their own characteristics, In order to in hardware resources utilization and system performance the compromise, In the FPGA design and realization process do the following optimization:(1) The whole design has adopted a variety of data flow control technologies, such as pipeline technology, ping-pong operation and string conversion technology and so on, to make a reasonable selection between speed and area according to hardware actual conditions, greatly improving the processing speed of system data;(2) using complementary operation to replace the multiplication of matched filter, has helped us overcome the problem of consuming time that happens in the hardware multiplication;(3) using the way of combining the separate frequency clock delay and delay line, greatly saves store resources lost by hardware data delay,by setting up the moment on effective data acquisition reasonable, we have overcome data jitter;(4) making full use of BlockRAM to realize the function of data storage and latch aids to avoid delay that is probably caused by data storage;(5) on the basis of systematic benchmarking clock,we distribute different clock frequency in line with different processing speed of different modules, reduce the processing delay through increasing the clock frequency to make each module work together harmoniously; (6) it adopts fixed point to express the fractional part during processing procedure, in which we make corresponding calibration and reasonable trade-offs for different data in different situation, as far as possible to improve the data processing speed without losing accuracy...