A Research Of Serial Interference Cancellation Multiuser Detection For CDMA System And It's Implementation Of FPGA

As the most effective and key technology to the suppression of multiple access interference in CDMA communication system,multi-user detection technology becomes the important research fields for communication scholars nowadays.In the situation of optimal and part of sub-optimal multi-user detection technology can not be realized in practice,serial interference cancellation(SIC)as one of the most important multi-user detection technology has won widely attention and research,which has advantages of good anti-jamming performance,simple structure,low computational complexity and easy to implementation.This paper has successively studied the analysis of theory and software simulation of the traditional single user detection algorithm and the SIC multi-user detection algorithm.Also,it analyzes receiving performance's changes of system in the condition of different ratio of spread spectrum for two kinds of detection algorithm and compares it.Then,observing and testing the improvement of SIC multi-user detection algorithm for bit error rate of the system.In this paper,two kinds of improved algorithm is put forward based on the deficiencies of SIC multi-user detection algorithm.One is that it proposes the better ways in view of that the instable accuracy of traditional bit amplitude estimation causes the instable results of decision during hard decision.The improved bit amplitude estimation method is not limited to the bit value itself,but updating a small part of it by using the previous bit amplitude estimation results to avoid a big difference between estimation value of amplitude and the real one which caused by signal mutation due to the interference during signal transmission.The other is that it optimizes the situation of the loss of bit information when estimates interference in asynchronous CDMA system.Different delay of time causes that the bit stream can not be completely aligned for difference user as the asynchronous signal transmission.Therefore,the estimation of interference is not complete because it can only estimate interference from the part of the same bit which transfers at the same time.In view of this kind of situation,the paper develops a algorithm of compensation for interference estimation based on traditional SIC detection algorithm to compensate interference from the former bit,which makes more accurate estimation of interference and better performance of system.In consider of the practical significance of SIC detection algorithm,the paper have completed the simulation and implementation of hardware for improved SIC algorithm in theend.And then debugging the hardware according to data compiled by the software of Signaltap from FPGA to make performance of bit error rate approach to the result of simulation of software.