Research And Implementation Of The Partial Parallel Interference Cancellation Detector

Because of multiple access interference (MAI) affecting the performance and capacity of the CDMA communication system seriously, inhibiting or eliminating the multiple access interference has been the hot topic of current research. With the ability to eliminate multiple access interference, multi-user detection techniques attract great attention. On the basis of the traditional detection techniques, multi-user detection technology regards MAI as useful information to take full advantage of the related information of all the users or part of the users, which is occupying a channel, and conduct a joint detection of detected users, in order to suppress or eliminate the MAI finally, thereby improving the performance and capacity of the CDMA communication system.This paper first analyzes the basic principle of multi-user detection algorithm, and researches principle and process of the partial parallel interference cancellation detector based on the Delta learning rule, combining characteristics of FPAG hardware implementation, presents a complete design scheme. The main work is as follows: (1) First, according to the principle of the algorithm, the algorithm is modular, self-directed under the in-depth step by step, the layers of refinement design.(2)In order to improve the speed of the system to process data, ping-pong operation, pipeline technology and string and conversion technology are adopted repeatedly in design, and a rational choice between speed and area is made, from the actual situation of the hardware.(3) In the matched filter design module, complementary operation instead of multiplication; in the interference cancellation factor adjustment module, the shift operation instead of a division operation on the arithmetic average operation. Meanwhile it saves hardware resources significantly.(4) The data with necessary delay, the delay line and clock frequency delay method of combining are adopt, which saves the hardware resources significantly. When collecting the data, in order to avoid data jitter and collect no valid data, it sets the effective data acquisition clock, to avoid the occurrence of this phenomenon.(5) In order to reduce the unnecessary high-frequency clock operation, to improve the stability of the system, according to the different modules of the data processing speed, on the basis of the system clock, it conducts the clock frequency relatively.(6) The use of Modelsim to each module in the functional simulation, simulation waveforms can meet the design requirements, and use Xilinx ISE XST on each module is synthesised.